Scan chain fault diagnosis

ABSTRACT

Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/852,892 filed on Mar. 28, 2013, now issued as U.S. Pat. No.8,560,904, which is a continuation of U.S. patent application Ser. No.13/225,168, filed Sep. 2, 2011, issued as U.S. Pat. No. 8,412,991, allof which is incorporated herein by reference in its entirety.

BACKGROUND

Scan testing of semiconductor devices is often used to check thefunctional operation of die. Scan testing employs scan chains arrangedon the die to test the logic connected therewith. During a scan test,the integrity of the scan chain is checked to determine whether the scanchain is functional prior to performing functional checks ofcombinational logic connected with the scan chain. However, it can bedifficult to determine the location of a defect in the scan chain,complicating failure analysis.

SUMMARY

Various embodiments are disclosed herein that relate to identifying areference scan cell locationally related to a fault condition exhibitedby a scan chain in which the reference scan cell is included. Forexample, one embodiment provides a method for identifying a referencescan cell, the method comprising, in a capture mode, outputtingcombinational logic values to scan cells in the scan chain so that scancell values for the scan cells are based on respective combinationallogic values, the combinational logic values electrically connected withthe scan chain. The example method further comprises, in a shift mode,sequentially determining the scan cell value for each scan cell, andidentifying as the reference scan cell a scan cell last determined to beat an expected logical state for that scan cell.

This Summary is provided to introduce a selection of concepts in asimplified form that are further described below in the DetailedDescription. This Summary is not intended to identify key features oressential features of the claimed subject matter, nor is it intended tobe used to limit the scope of the claimed subject matter. Furthermore,the claimed subject matter is not limited to implementations that solveany or all disadvantages noted in any part of this disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a flowchart for a method of detecting a potential scanchain defect condition and identifying a reference scan celllocationally related to the defect condition according to an embodimentof the present disclosure.

FIG. 2 shows a flowchart for a method of a detection phase according toan embodiment of the present disclosure.

FIG. 3A schematically shows an example test vector prior to beingshifted into an example scan chain during scan chain defect conditionidentification according to an embodiment of the present disclosure.

FIG. 3B schematically shows the scan chain of FIG. 3A at a time afterthe test vector has been shifted into the scan chain.

FIG. 3C schematically shows the scan chain of FIG. 3B at a time afterthe test vector has been shifted out of the scan chain and the scan cellvalues have been sequentially determined

FIG. 4 shows a flowchart for a method of an identification phaseaccording to an embodiment of the present disclosure.

FIG. 5 schematically shows a reference scan cell identified according toan embodiment of the present disclosure.

FIG. 6 schematically shows a reference scan cell identified according toanother embodiment of the present disclosure.

FIG. 7 shows, in tabular form, a method of determining whether to updatean identity of a reference scan cell according to an embodiment of thepresent disclosure.

FIG. 8 shows a flowchart for a method of outputting reference scan cellinformation according to an embodiment of the present disclosure.

FIG. 9 shows a flowchart for another method of an identification phaseaccording to an embodiment of the present disclosure.

FIG. 10 schematically shows a failure analysis system according to anembodiment of the present disclosure.

DETAILED DESCRIPTION

Scan testing of semiconductor devices is often used to check thefunctional operation of die prior to shipping and, in some cases, duringfailure analysis of non-functional semiconductor devices. In somedesigns, scan may be used to test more than 98% of the architecturalstructures present on the die. The number of scan chains providing scancoverage has increased along with the expanding number of devicespresent in modern designs. Consequently, it is becoming more common formanufacturing defects to affect the scan chains.

Scan tests are typically performed by providing a test vector to a scanchain that provides test coverage to a portion of the die. Typically, ascan test includes a chain test used to check the integrity of the scanchain. In the chain test, a test vector is shifted through a scan chain.If the test vector output matches the test vector input, the scan testgoes on to check the combinational logic connected with that scan chain.The result of the evaluation may be used to determine whether thosecombinational logic cells may include manufacturing defects that inhibitproper device function.

Because data is shifted through a scan chain serially from the input tothe output during the chain test, it is difficult to locate a defectwithin the scan chain. One approach for diagnosing a defect in a scanchain includes powering on the device in a known state after a reset, sothat a known value is loaded into various state elements of the device,such as flip-flops and the like. Then, when the scan test is executed,the known state is the first to be shifted out of the scan chain. Bycomparing the observed output of the scan chain to the output of a knownnon-defective scan chain, it may be possible to exclude some possibledefect locations. Such approaches may be hindered by the particularreset state selected and by the inherent one-shot nature of the resetstate.

Other approaches may include fault simulation of the scan chain. Suchapproaches are computationally intensive and frequently requireextensive knowledge of the logical design of the device provide byelectronic design automation software. Because electronic designautomation software is often tuned toward device design rather thandefect diagnosis, it may require the involvement of device architectsrather than failure analysis engineers, potentially adding to theexpense of the excursion and delaying other projects.

The disclosed embodiments relate to identifying a reference scan celllocationally related to a fault condition exhibited by a scan chain inwhich the reference scan cell is included. For example, a method foridentifying a reference scan cell is disclosed, the method comprising,in a capture mode, outputting combinational logic values to scan cellsin the scan chain so that scan cell values for the scan cells are basedon respective combinational logic values, the combinational logic valueselectrically connected with the scan chain. The example method furthercomprises, in a shift mode, sequentially determining the scan cell valuefor each scan cell, and identifying as the reference scan cell a scancell last determined to be at an expected logical state for that scancell.

A scan chain represents a logical path between a scan chain input, wherea test vector is input, and a scan chain output, where the test vectoris output for evaluation. Scan chains provide input to and receiveoutput from combinational logic cells connected to the scan chains viascan cells. For clarity, the embodiments described herein refer totesting a single scan chain. However, it will be appreciated that anysuitable number of scan chains may be tested without departing from thescope of the present disclosure. For example, in some embodiments, everyscan chain on a device may be tested. In some other embodiments, only asubset of scan chains on a device may be tested, such as insystem-on-a-chip devices.

FIG. 1 shows a flowchart for an embodiment of a method 100 for detectinga candidate scan chain defect condition and identifying a reference scancell in the scan chain that may be used to potentially locate, inlogical and/or physical space, a defect giving rise to the detecteddefect condition. As shown in FIG. 1, method 100 is broadly divided intodetection and identification phases for illustrative purposes only, andis not intended to be limiting in any way.

At 102, method 100 comprises a detection mode configured to detect acandidate scan chain defect. Virtually any suitable scan chain defectcondition may be detected according to the disclosed embodiments.Non-limiting examples of scan chain defect conditions that may bedetected in detection mode 102 include a candidate stuck-at condition, acandidate slow to rise and/or slow to fall condition, and a candidatecycle early and/or cycle late condition. Examples of such defectconditions will be described in more detail below.

FIG. 2 shows a flowchart for an embodiment of a method 200 of detectinga scan chain defect. Method 200 comprises, at 202, sequentiallyassigning a scan cell index to each scan cell according to a scan cellorder. By assigning each scan cell a scan cell index, the valuesassigned to the various scan cells within the scan chain may be trackedduring the shift and capture operations described below. Each scan cellis assigned a scan cell index that is different from the scan cell indexof any other scan cell, so that scan cells may be identified accordingto the scan cell index associated with the scan cell. The scan cellindices may be assigned in any suitable manner without departing fromthe scope of the present disclosure. For example, in some embodiments,scan cell indices may be ordered from a position where test vectorvalues are shifted out of the scan chain (i.e., a scan out position) or,alternatively, via a position where test vector values are shifted intothe scan chain (i.e., a scan in position). In some embodiments, the scancell indices may be ordered according to an order in which scan cellsare arranged in the scan chain (i.e., a scan cell order), though anysuitable order may be used to assign the scan cell indices withoutdeparting from the scope of the present disclosure.

At 204, method 200 comprises shifting a test vector into the scan chain.In some embodiments, a test vector may be shifted into the scan chain byenabling a scan enable setting (e.g., by setting a scan enable settingto 1), placing the device into a shift mode. At each clock cycle, asuccessive bit of the test vector is shifted into the scan chain.Previously entered bits are shifted into the scan chain in a sequentialmanner until the entire scan chain is populated by the test vectorand/or until the entire test vector is shifted into the scan chain.

Because the embodiments of method 200 described herein are directed atdetecting candidate defects in the scan chain and not defects arising inthe combinational logic, it may be helpful to observe the logicalfunction of the scan chain without the confounding effects of thelogical output of the combinational logic electrically connected to thescan chain. Thus, the test vector is shifted out of the scan chainwithout capturing the logical behavior of the combinational logic. Inthe embodiment shown in FIG. 2, method 200 comprises, at 206,sequentially determining the scan cell value for each scan cell withoutoutputting combinational logic values from the combinational logic cellsto the scan cells. In some embodiments, the test vector may be shiftedout of the scan chain by enabling a scan enable setting, placing thedevice into a shift mode. At each clock cycle, a successive bit of thetest vector is shifted out of the scan chain and a value is determinedPreviously entered bits are shifted out of the scan chain in asequential manner until the entire content of the scan chain has beenshifted out of the scan chain. By tracking the number of clock cycles,any determined value of may be matched, via the scan cell index, to thescan cell associated with that value. While shifting the test vectorinto the scan chain at 204 and determining the scan cell values at 206are described above as separate events for illustrative purposes, itwill be appreciated that, in some embodiments, shifting the test vectorinto the scan chain at 204 and determining the scan cell values at 206may occur concurrently or sequentially without the device exiting andre-entering a shift mode.

At 208, method 200 comprises identifying a candidate scan chain defectcondition based on the scan cell values so determined. Identification ofa candidate scan chain defect condition may be accomplished by virtuallyany suitable approach. For example, the non-limiting selection ofcandidate scan chain defect conditions described above may be identifiedvia comparison to a look-up table, setting flag, and so on.

FIGS. 3A-C schematically show an embodiment of a scan chain includingeight scan cells at three successive times to illustrate how a candidatescan chain defect may be identified according to an embodiment of method200. It will be appreciated that the example scan chain and test vectorin FIGS. 3A-C are simplified for illustrative purposes, and that theexample is not intended to be limiting in any sense.

The embodiment of the scan chain shown in FIGS. 3A-C includes eight scancells, each assigned an individual scan cell index running from 1 to 8in order starting from the scan out position and ending at the scan inposition. The scan cell indices depicted in FIGS. 3A-C are illustratedas integers, though it will be appreciated that a scan cell index mayinclude virtually any suitable identifier, including alphanumericcharacters, digital bit addresses, and the like.

In the example shown in FIGS. 3A-C, a stuck-at high condition is shownbetween scan cells 5 and 4. As used herein, a stuck-at condition is usedto describe a fault or a fault model where a signal output from a logiccell (such as a scan cell) is observed to have the same value regardlessof values input to that logic cell, so that the output of that logiccell appears to be “stuck at” that same value. For example, a stuck-atcondition may be used to describe a logic cell that is observed toreturn a logic high (i.e., 1) or a logic low (i.e., 0) regardless ofinput provided to the cell and despite expected behavior for that cellto the contrary. The stuck-at high condition shown in FIGS. 3A-C ismerely provided as an illustrative example of how any suitable candidatescan chain defect condition may be detected according to the embodimentsdescribed herein.

FIG. 3A shows a test vector ready to be shifted into the scan chain. InFIG. 3A, the test vector is illustrated as a pattern of high and lowsignals “0011” that is configured to be repeated as the test vector isshifted into the scan chain. It will be appreciated that the test vectorshown in FIG. 3A is merely an example test vector and that virtually anysuitable test vector may be employed without departing from the presentdisclosure. The test vector shown in FIG. 3A is shown at the scan inlocation at an arbitrary reference time zero.

FIG. 3B depicts the example of FIG. 3A after 8 clock cycles, when afirst portion of the test vector has been shifted in and each scan cellof the scan chain is populated by a value from the test vector. Becausethe combinational logic should not affect the value of the scan cellsduring the shift mode, the process of shifting the test vector into andout of a non-defective scan chain should not alter the test vector.Thus, for the test vector “00110011,” scan cells indexed 8 through 1would be expected to have values, of 0, 0, 1, 1, 0, 0, 1, and 1,respectively. However, because the example scan chain shown in FIG. 3Bincludes a stuck-at high fault that causes the output of scan cell 5 tobe set to a logic high regardless of the input to scan cell high,shifting the test vector into the scan chain causes values stored inscan cells indexed 4 through 1 to each have a value of 1.

FIG. 3C depicts the example of FIG. 3B after 8 clock cycles, when afirst portion of the test vector has been shifted out of the scan chain.Because the example scan chain shown in FIG. 3C includes the stuck-athigh fault, shifting the test vector out of the scan chain causes valuesstored in scan cells indexed 4 through 1 to each have a value of 1 forthe same reason described above. Further, shifting the test vector outof the scan chain causes the values stored in scan cells indexed 8through 5 in FIG. 3B to pass through scan cell 5 causing those values tobe output as logic high values. Consequently, the sequentiallydetermined value for the test vector output at FIG. 3C is “11111111,”instead of the expected value of “00110011.”

FIG. 3C also shows an example of how a scan cell index may be associatedwith a scan cell value. As shown in FIG. 3C, at the eighth clock tickafter the test vector is shifted out, the value of 1 is associated withscan cell index 8. In some embodiments, such values may be stored in afile by association to the time and/or the sequence in which the valuewas determined.

Based on the difference between the observed test vector output (e.g.,the sequentially determined values for the scan cells) and the expectedtest vector output, a candidate scan chain defect condition may beidentified. In the example depicted in FIGS. 3A-C, a candidate stuck-athigh condition is identified. Table 1 presents a non-limiting list ofcandidate scan chain defect conditions that may be identified based onrepresentative differences between an example test vector and scan chainoutput indicative of the various scan chain defect conditions presentedtherein. It will be understood that the examples presented in Table 1are merely provided for illustrative purposes, and that they are notintended to limit the scope of the scan chain defect conditions that maypotentially be identified and/or the manner by which such conditions maybe identified in any way.

TABLE 1 Candidate Scan Chain Defect Expected Test Observed TestCondition Vector Output Vector Output Stuck-at High 00110011001100111111111111111111 Stuck-at Low 0011001100110011 0000000000000000 Slow toRise 0011001100110011 0001000100010001 Slow to Fall 00110011001100110011101110111011 Cycle Early 0011001100110011 0110011001100110 CycleLate 0011001100110011 0001100110011001

Turning back to FIG. 1, once a candidate scan chain defect condition hasbeen identified, method 100 enters an identification phase comprising acapture mode 104, a shift mode 106, and an output mode 108. While thedetection phase described above with respect to FIGS. 2 and 3A-C isdirected at classifying the behavior of the scan chain defect byobserving the output of the defective scan chain during a test withoutthe confounding effects of the combinational logic, portions of theidentification phase described below are directed at determiningcontradictions between observed logic tests (e.g., tests that checklogical function of the combinational logic electrically connected withthe defective scan chain) and expected output from those logic tests.These contradictions may be used to identify a reference scan cell thatmay be output for display and/or to help localize the candidate defectin logical and/or physical space as described in more detail below.

As used herein, a reference scan cell refers to a scan cell lastdetermined to be at an expected logical state for that scan cell. Putanother way, a reference scan cell represents, for a specific logicaltest, the last observable working scan cell in the order in which thescan cell values are sequentially determined.

Determination of a working scan cell may be made by comparison of theoutput of the scan cell to an expected value for that scan cell, so thatthe last scan cell to return a value that matches the expected value isidentified as the reference scan cell. It will be appreciated that theexpected value may be any virtually any suitable value. For example, insome embodiments, the expected value may be a value that is indicativeof proper logical function for a portion of combinational logic cellsassociated with that scan cell. In some other embodiments, the expectedvalue may be a value that is selected as a value that is opposite avalue that would normally be returned by a scan cell influence by thecandidate defect condition. For example, because a stuck-at high defectcondition would normally return a 1, the last cell to return an expectedvalue of a 0 may be identified as the reference cell. Accordingly, insuch embodiments it may be possible to identify the reference cell evenin situations where logical faults elsewhere in the combinational logiccells may coincidentally lead to scan chain output indicating improperlogical function of those combinational logic cells.

In some embodiments, scan cell values may be determined according to ascan cell order from a scan out position to a scan in position; FIG. 3Cis an example of such an embodiment. In such embodiments, the referencescan cell would be positioned closer to the scan in position than anyother working scan cell (e.g., than any other scan cell having anobserved value that matches an expected value for that scan cell forthat logical test). It will be understood that the reference scan cellmay be translated into virtually any other suitable reference cell orlogical domain without departing from the scope of the presentdisclosure.

FIG. 4 shows a flowchart for an embodiment of a method 400 ofidentifying a reference scan cell. At 402, method 400 comprises shiftinga test vector into the scan chain. In some embodiments, the device maybe placed into the shift mode by enabling a scan enable setting so thatthe test vector may be shifted into the scan chain as described above.

In the embodiment shown in FIG. 4, method 400 comprises, at 404,outputting combinational logic values to scan cells in the scan chain sothat scan cell values for the scan cells are based on respectivecombinational logic values in a capture mode. Because method 400 isdirected at identifying the reference scan cell using contradictionsdetermined from observed logic tests, once the test vector is shiftedinto the scan chain, the scan chain is placed in a capture modeconfigured to apply the test vector to the combinational logicelectrically connected with the scan chain. In some embodiments, thescan chain may be placed into a capture mode by disabling a scan enablesetting (e.g., by setting a scan enable setting to 0). Once the testvector is applied, a subsequent clock cycle causes the combinationallogic cells to generate values that are then output to the scan chain,so that the scan cells capture the logical behavior of the combinationallogic.

At 406, method 400 comprises sequentially determining the scan cellvalue for each scan cell in a shift mode. Thus, the values generated bythe combinational logic cells and output to the scan cells are shiftedout as described above. A scan cell index may be associated with one ormore of the determined values so that individual and/or groups of scancells may be identified via the associated scan cell indices. Forexample, a list of scan cell indices associated with determined valuesthat do not match values expected to be observed may be used to identifyrespective scan cells providing those mismatched values.

At 408, method 400 comprises determining whether to apply differentcombinational logic values to the scan chain. In some embodiments,determination at 408 may include a selection of a particular test vectorto be applied to the scan chain. If it is judged that additionalcombinational logic values are to be applied, method 400 returns to 402.Additional combinational logic values may be provided by shiftingdifferent test vectors into and out of the scan chain. By providingdifferent test vectors to the combinational logic cells for a given scanchain and comparing the scan cell indices of the respective referencescan cells subsequently identified as described in more detail below, itmay be possible to discriminate intermittent defect conditions fromconstant defect conditions and/or to identify a reference scan cell fora defect condition that is closest to the scan chain input for the testvectors provided. For example, in some embodiments, thirty or moredifferent test vectors may be provided, though fewer test vectors may beprovided in some other embodiments.

Because a plurality of test vectors may be provided to test differentportions of the combinational logic connected with the scan chain,variation within the provided test vectors may provide an approach toreduce errors that may be introduced by unrelated functional faultswithin the combinational logic cells. Additionally or alternatively,using a plurality of test vectors and, if appropriate, updating theidentity of the reference scan cell in response, may provide acomparatively faster or more accurate approach to identifying thelocation of the scan cell defect relative to the reset and/or simulationtechniques described above.

If additional test vectors are not applied, method 400 continues to 410,comprising identifying as the reference scan cell a scan cell lastdetermined to be at an expected logical state for that scan cell. Itwill be appreciated that the specific manner by which the reference scancell is identified may vary depending on the candidate scan cell defectcondition. For example, for a scan chain exhibiting a stuck-at highdefect condition, the last observed scan cell to exhibit an expectedlogic low state may be identified as the reference scan cell. In anembodiment where scan cell values are sequentially determined byshifting a test vector out of a scan chain from a position opposite of aposition from which the test vector is shifted in, the reference scancell may correspond to a position in the logical flow of the scan chainthat is closer to the scan chain input than any other observablyfunctional scan cell.

FIG. 5 schematically shows an embodiment of a scan chain having astuck-at high defect condition between scan cells 5 and 4. In theembodiment shown in FIG. 5, a test vector “00110011” was shifted intothe scan chain during an earlier shift mode (not shown). During acapture mode, values generated by combinational logic cells are outputto scan cells indexed 8 through 1 so that those scan cells have valuesof 0, 0, 1, 0, 0, 1, 0, and 1, respectively. During a second shift mode,the values in the scan chain are shifted out and sequentiallydetermined. Because of the positioning of the stuck-at high defect, theactual output of the scan chain is observed as “11110101” instead of theexpected output of “00100101.”

The example shown in FIG. 5 illustrates how the differences between theexpected output and the observed output of the scan chain may be used toidentify the reference scan cell. As explained above, the identity ofthe reference scan cell may be determined by comparing the sequentiallydetermined values of the scan cells shifted out of the scan chain withvalues expected to be output from the scan chain. In this example,because the candidate scan chain defect condition is a stuck-at highcondition that normally returns a 1, the expected value used to identifythe reference scan cell is 0. Accordingly, FIG. 5 shows that scan cell4, being the last scan cell to have a value determined to be at theexpected logical state of 0, is identified as the reference scan cell.

In some embodiments, the expected value may comprise a plurality ofvalues output by the scan chain. For example, in some embodiments, thereference scan cell may be identified from a pair of scan cells lastexhibiting an expected transition between two logical states. In suchembodiments, the reference scan cell may be identified as the scan cellof that pair that is closer to the scan chain input. By comparing aplurality of values from the observed scan chain output to a pluralityof expected values, it may be possible to identify reference scan cellsrelated to transition delay faults such as a slow to rise faultconditions, a slow to fall fault condition, a cycle early faultcondition, and a cycle late fault condition. Such transition delayfaults may indicate the existence of a hold time violation caused by adefect in a clock input to a scan cell to which the transition delay istraceable. Alternatively, such transition delay faults may indicate theexistence of a setup time violation caused by a defect in a data inputto a scan cell to which the transition delay is traceable.

For example, FIG. 6 schematically shows an embodiment of a scan chainhaving a slow to rise defect condition between scan cells 5 and 4. Asused herein, a slow to rise condition is used to describe a fault or afault model where a signal output from a logic cell (such as a scancell) exhibits a delay in a transition from a logic low to a logic highstate, so that the output of that logic cell remains at a logic lowstate by one or more clock cycles compared to a normally operating cellbefore transitioning to the logic high state. However, a subsequenttransition from the logic high state to the logic low state does notappear delayed in a slow to rise defect condition. Thus, a slow to risecondition only manifests as a delay in the rising transition, while thefalling transition is undelayed. A non-limiting example of slow to risebehavior may be found in Table 1.

In the example shown in FIG. 6, a test vector “00110011” was shiftedinto the scan chain during an earlier shift mode (not shown). During acapture mode, values generated by combinational logic cells are outputto scan cells indexed 8 through 1 so that those scan cells have valuesof 0, 0, 1, 0, 0, 1, 0, and 1, respectively. During a second shift mode,the values in the scan chain are shifted out and sequentiallydetermined. Because of the positioning of the slow to rise defect, theactual output of the scan chain is observed as “00000101” instead of theexpected output of “00100101.” The reference scan cell is identified bycomparing the sequentially determined values of the scan cells shiftedout of the scan chain with values expected to be output from the scanchain. Because the slow to rise condition shown in the exampleillustrated in FIG. 6 would normally return a pair of logic low valuesinstead of a transition from a 0 to a 1, identifying the reference scancell includes identifying the last transition from a 0 to a 1 that isindicative of proper logical function for a portion of combinationallogic cells associated with that scan cell. Put another way, the lasttransition from a 0 to a 1 that matches an expected transition from a 0to a 1 will be used to identify the reference scan cell. In the exampleshown in FIG. 6, the last transition from 0 to 1 corresponds to thevalues in scan cells 3 and 4, which are determined in sequentially inthat order. Once the last transition is identified, the reference scancell is identified by selecting the scan cell of that pair of scan cells(e.g., scan cells 3 and 4) that is closer to the scan chain input (i.e.,scan cell 4).

A similar approach may be used to identify reference scan cells forother transition delay faults. For example, the approach described abovefor identifying a reference scan cell for a slow to rise condition mayalso be employed to identify a reference scan cell for a cycle latecondition. As used herein, a cycle late condition describes a fault or afault model where a signal output from a logic cell exhibits a delay ina transition from a logic low state to a logic high state, so that theoutput of that logic cell remains at a logic low state by one or moreclock cycles compared to a normally operating cell before transitioningto the logic high state, and where a subsequent transition from thelogic high state to a logic low state is also delayed by one or moreclock cycles before transitioning to a logic low state.

As another example, a last transition from a 1 to a 0 may be used toidentify a reference scan cell for a slow to fall condition. As usedherein, a slow to fall condition describes a fault or a fault modelwhere a signal output from a logic cell exhibits a delay in a transitionfrom a logic high state to a logic low state, so that the output of thatlogic cell remains at a logic high state by one or more clock cyclescompared to a normally operating cell before transitioning to the logiclow state while a subsequent transition from the logic low state to alogic high state is not delayed.

As yet another example, the approach described above for identifying areference scan cell for a slow to fall condition may also be employed toidentify a reference scan cell for a cycle early condition. As usedherein, a cycle early condition describes a fault or a fault model wherea signal output from a logic cell exhibits a delay in a transition froma logic high state to a logic low state, so that the output of thatlogic cell remains at a logic high state by one or more clock cyclescompared to a normally operating cell before transitioning to the logiclow state, and where a subsequent transition from the logic low state toa logic high state is also delayed by one or more clock cycles beforetransitioning to a logic high state.

While the examples above describe transitions between two logic states,it will be appreciated that any suitable logic transition sequencecomprising any suitable number of bits may be used to identify areference scan cell associated with a candidate scan chain defectwithout departing from the scope of the present disclosure. For example,in some embodiments, an alternating three-bit logic sequence may be usedto identify a reference scan cell associated with an open defect (e.g.,a defect mode that may mimic an incomplete circuit). For example,because an open defect may be affected by surrounding logic cells and/orwires via capacitive coupling, it is possible that a scan cellexhibiting an open defect may not produce a transition from a 0 to a 1to a 0 when a physically adjacent wire is in a logic low state. Thus, insome of such embodiments, a transition from a 0 to a 1 to a 0 may beused to identify a reference scan cell associated with an open defect.

Returning to FIG. 4, in some embodiments, identifying the reference scancell at 410 may include determining whether to update an identity of thereference scan cell. In some embodiments, a determination about whetherto update the identity of the reference scan cell may be made based oncomparisons of scan cell indices of respective reference scan cellsidentified as the result of a plurality of different test vectorsapplied to the scan chain. For example, the identity of the referencescan cell may be updated if a scan cell identified as the reference scancell is determined to be closer to a scan chain input than a scan cellpreviously identified as the reference scan cell.

FIG. 7 shows a table of scan cell values output from an example scanchain from four successive example tests using four different exampletest vectors labeled tests 1 through 4 according to the embodimentsdescribed herein. For reference, a list of scan cell indices associatedwith the scan cell values output from the scan chain is provided along apositional indication of the scan chain input and the scan chain outputrelative to those cells. As shown in FIG. 8, a stuck-at low conditionexists between scan cells 4 and 5 in the scan chain. Accordingly, thereference scan cell will be identified with reference to the lastdetermined logic high state in a particular test. For example, scan cell1 is identified as the reference scan cell in test 1.

In the embodiment shown in FIG. 7, the identity of the reference scancell is updated if it is determined that the reference scan cell iscloser to the scan cell input than previously identified reference scancells. For example, scan cell 3 is identified as the reference scan cellin test 2. Because scan cell 3 is closer to the scan input location thanscan 1, the identity of the reference scan cell is updated to scan cell3. The identity of the reference scan cell is updated again after test3, where scan cell 4 is identified as the reference scan cell. However,the identity of the reference scan cell is not updated after test 4because the last scan cell to have a logical state of 1 is scan cell 3,which is not closer to the scan chain input than scan cell 4.

Continuing with FIG. 4, method 400 includes, at 412, outputting thereference cell identity in an output mode. FIG. 8 shows an embodiment ofa method 800 for outputting a reference cell identity. Method 800includes, at 802, obtaining a scan cell instance name for the referencescan cell. In some embodiments the scan cell instance name may beobtained with reference to the scan cell index for that scan cell. Forexample, in some of such embodiments, an instance name may be obtainedby looking up the scan cell index associated with the scan cell, eitherdirectly or by suitable translation, in a standard test interfacelanguage (STIL) file associated with the scan chain. However, it will beappreciated that virtually any suitable manner of obtaining a scan cellinstance name in virtually any suitable format may be employed withoutdeparting from the scope of the present disclosure.

At 804, method 800 includes outputting the scan cell instance name forthe reference scan cell for display. In some embodiments, otherinformation may be output for display, including the candidate scanchain defect condition, previously identified reference scan cells,statistical information related to various scan cells successivelyidentified as the reference scan cell, and the like. Further, in someembodiments, logical and/or physical layout information associated withthe reference scan cell instance name may be output. For example, in onescenario, a portion of the logical and/or physical layout of the scanchain including the reference scan cell may be output for display.

Because defects may actually exist on a net connecting another scan cellto the reference scan cell, in some embodiments the identity of anotherscan cell and/or a clock source that provides input to the referencescan cell may be output. In some scenarios the input of the particularscan cell and/or the clock source may be directly connected to the inputof the reference scan cell. Accordingly, in some embodiments, method 800may include, at 806, identifying a particular scan cell and/or aparticular clock source providing input to the reference scan cell,which may include identifying a particular scan cell and/or a particularclock source having an input directly connected to an input of thereference scan cell. At 808, method 800 includes obtaining a scan cellinstance name for the particular scan cell, such as by using a scan cellindex for that particular scan cell. Then, at 810, method 800 mayinclude outputting the scan cell instance name for the particular scancell and/or the identity of the clock source providing input to thereference scan cell for display.

It will be appreciated that methods described herein are provided forillustrative purposes only and are not intended to be limiting.Accordingly, the methods shown in the figures and described herein mayinclude additional or alternative processes in some embodiments, and insome embodiments, some processes may be reordered or omitted withoutdeparting from the scope of the present disclosure.

For example, FIG. 9 shows a flowchart for an embodiment of a method 900of identifying a reference scan cell comprising shifting a test vectorinto a scan chain at 902, outputting combinational logic values to scancells in the scan chain so that scan cell values for the scan cells arebased on respective combinational logic values at 904, sequentiallydetermining a scan cell value for each scan cell at 906, and identifyingas a reference scan cell a scan cell last determined to be at anexpected logical state for that scan cell at 908. At 910, method 900includes determining whether to apply different combinational logicvalues. In some embodiments, determination at 910 may include aselection of a particular test vector to be applied to the scan chain.If it is judged that additional combinational logic values are to beapplied, such as for the reasons described above, method 900 returns to902. If additional combinational logic values are not applied, method900 continues to 912 where the reference cell identity is output in anoutput mode. In some embodiments, judgment and selection of a particulartest vector may depend, at least in part, on the identification of thereference scan cell at 906, so that the identity of the reference scancell may influence selection of one or more successive test vectors.Such approaches may assist with defect localization when used with testhardware configured to store less capture data than may be generatedfrom the set of test vectors input to the scan chain.

Further, it will be appreciated that the methods described herein may besuitably performed by virtually any suitable hardware and/or software.FIG. 10 schematically shows an embodiment of a failure analysis system1000 that may be used to detect a scan chain defect condition andidentify a reference scan cell related to that defect condition. Failureanalysis system 1000 includes a computing system 1002 having adata-holding subsystem 1004, a logic subsystem 1006, and a displaysubsystem 1008. In the embodiment depicted in FIG. 10, computing system1002 is in operative communication with suitable test equipment 1050configured to perform logic function tests on a semiconductor device.However, it will be appreciated that test equipment 1050 may be optionalin some embodiments. For example, in some embodiments the processesdescribed herein may be performed by computing system 1002 using datapreviously collected by suitable test equipment without computing system1002 being in operative communication with that test equipment.

Instructions held in data-holding subsystem 1004 and executed by logicsubsystem 1006 may be used to perform various method described herein.Data-holding subsystem 1004 may include one or more physical,non-transitory, devices configured to hold data and/or instructionsexcluding a signal per se that are executable by logic subsystem 1006 toimplement the methods and processes described herein. For example,data-holding subsystem 1004 may include one or more hard disks, flashdrives, memory devices, caches, and/or registers configured to hold dataand/or instructions.

Logic subsystem 1006 may include one or more physical devices configuredto execute one or more instructions stored in data-holding subsystem1004. For example, logic subsystem 1006 may include one or moreprocessors that are configured to execute software instructions.

Display subsystem 1008 may be used to present the output describedherein in a manner so that the output may be transformed into a visuallycognizable form. Display subsystem 1008 may include any suitable displaydevice, which may be combined in a shared enclosure with data-holdingsubsystem 1004 and logic subsystem 1006 or which may be include one ormore peripheral display devices.

FIG. 10 also shows removable computer-readable storage media 1010, whichmay be used to store and/or transfer data and/or instructions executableto implement the methods and processes described herein. It will beappreciated that any suitable removable computer-readable storage mediaexcluding a signal per se may be employed without departing from thescope of the present disclosure. Non-limiting examples include DVDs,CD-ROMs, floppy discs, and flash drives.

It is to be understood that the configurations and/or approachesdescribed herein are exemplary in nature, and that these specificembodiments or examples are not to be considered in a limiting sense,because numerous variations are possible. The specific routines ormethods described herein may represent one or more of any number ofprocessing strategies. As such, various acts illustrated may beperformed in the sequence illustrated, in other sequences, in parallel,or in some cases omitted. Likewise, the order of the above-describedprocesses may be changed.

The subject matter of the present disclosure includes all novel andnonobvious combinations and subcombinations of the various processes,systems and configurations, and other features, functions, acts, and/orproperties disclosed herein, as well as any and all equivalents thereof.

The invention claimed is:
 1. A method for testing an integrated circuit,comprising the steps of: shifting a test vector into a scan chain of theintegrated circuit; outputting combinational logic values to scan cellsin the scan chain so that scan cell values for the scan cells are basedon respective combinational logic values, the combinational logic valuesbeing generated by combinational logic cells electrically connected withthe scan chain; sequentially determining the scan cell value for eachscan cell; identifying as a reference scan cell a scan cell lastdetermined to be at an expected logical state for that scan cell;determining whether there is a candidate reference cell that is closerto an input end of the scan chain than the identified reference scancell; and in the case that there is a candidate reference cell that iscloser to an input end of the scan chain than the identified referencescan cell, replacing the identified reference cell with the candidatereference cell as a new identified reference cell for assessing a defectin the integrated circuit.
 2. The method of claim 1 in which thereference scan cell is identified from scan cells including a pair ofscan cells last exhibiting an expected transition between two logicalstates, wherein the reference scan cell is identified as the scan cellof the pair that is closer to the input end of the scan chain.
 3. Themethod of claim 1 in which scan cell values are sequentially determinedby shifting a test vector out of a scan chain from a position opposite aposition from which the test vector is shifted in and the reference scancell corresponds to a position in a scan chain that is closer to theinput end of the scan chain than any other scan cell that is observablyfunctional.
 4. The method of claim 1 further including sequentiallyassigning to each scan cell a scan cell index according to a scan cellorder, the scan cell index assigned to each scan cell being differentfrom the scan cell index of each other scan cell.
 5. The method of claim4 further including determining whether to identify an updated referencescan cell based on a comparison of scan cell indices of respectivereference scan cells identified from plural test vectors applied to ascan chain.
 6. The method of claim 5 in which an updated reference scancell is identified if a scan cell identified as the reference scan cellis determined to be closer to a scan chain input than a scan cellpreviously identified as the reference scan cell.